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-rw-r--r--hw/openrisc/Kconfig18
-rw-r--r--hw/openrisc/boot.c119
-rw-r--r--hw/openrisc/cputimer.c165
-rw-r--r--hw/openrisc/meson.build7
-rw-r--r--hw/openrisc/openrisc_sim.c371
-rw-r--r--hw/openrisc/virt.c571
6 files changed, 1251 insertions, 0 deletions
diff --git a/hw/openrisc/Kconfig b/hw/openrisc/Kconfig
new file mode 100644
index 00000000..97af258b
--- /dev/null
+++ b/hw/openrisc/Kconfig
@@ -0,0 +1,18 @@
+config OR1K_SIM
+ bool
+ select SERIAL
+ select OPENCORES_ETH
+ select OMPIC
+ select SPLIT_IRQ
+
+config OR1K_VIRT
+ bool
+ imply PCI_DEVICES
+ imply VIRTIO_VGA
+ imply TEST_DEVICES
+ select PCI
+ select PCI_EXPRESS_GENERIC_BRIDGE
+ select GOLDFISH_RTC
+ select SERIAL
+ select SIFIVE_TEST
+ select VIRTIO_MMIO
diff --git a/hw/openrisc/boot.c b/hw/openrisc/boot.c
new file mode 100644
index 00000000..007e80cd
--- /dev/null
+++ b/hw/openrisc/boot.c
@@ -0,0 +1,119 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * QEMU OpenRISC boot helpers.
+ *
+ * (c) 2022 Stafford Horne <shorne@gmail.com>
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "exec/cpu-defs.h"
+#include "elf.h"
+#include "hw/loader.h"
+#include "hw/openrisc/boot.h"
+#include "sysemu/device_tree.h"
+#include "sysemu/qtest.h"
+#include "sysemu/reset.h"
+
+#include <libfdt.h>
+
+#define KERNEL_LOAD_ADDR 0x100
+
+hwaddr openrisc_load_kernel(ram_addr_t ram_size,
+ const char *kernel_filename,
+ uint32_t *bootstrap_pc)
+{
+ long kernel_size;
+ uint64_t elf_entry;
+ uint64_t high_addr;
+ hwaddr entry;
+
+ if (kernel_filename && !qtest_enabled()) {
+ kernel_size = load_elf(kernel_filename, NULL, NULL, NULL,
+ &elf_entry, NULL, &high_addr, NULL, 1,
+ EM_OPENRISC, 1, 0);
+ entry = elf_entry;
+ if (kernel_size < 0) {
+ kernel_size = load_uimage(kernel_filename,
+ &entry, NULL, NULL, NULL, NULL);
+ high_addr = entry + kernel_size;
+ }
+ if (kernel_size < 0) {
+ kernel_size = load_image_targphys(kernel_filename,
+ KERNEL_LOAD_ADDR,
+ ram_size - KERNEL_LOAD_ADDR);
+ high_addr = KERNEL_LOAD_ADDR + kernel_size;
+ }
+
+ if (entry <= 0) {
+ entry = KERNEL_LOAD_ADDR;
+ }
+
+ if (kernel_size < 0) {
+ error_report("couldn't load the kernel '%s'", kernel_filename);
+ exit(1);
+ }
+ *bootstrap_pc = entry;
+
+ return high_addr;
+ }
+ return 0;
+}
+
+hwaddr openrisc_load_initrd(void *fdt, const char *filename,
+ hwaddr load_start, uint64_t mem_size)
+{
+ int size;
+ hwaddr start;
+
+ /* We put the initrd right after the kernel; page aligned. */
+ start = TARGET_PAGE_ALIGN(load_start);
+
+ size = load_ramdisk(filename, start, mem_size - start);
+ if (size < 0) {
+ size = load_image_targphys(filename, start, mem_size - start);
+ if (size < 0) {
+ error_report("could not load ramdisk '%s'", filename);
+ exit(1);
+ }
+ }
+
+ if (fdt) {
+ qemu_fdt_setprop_cell(fdt, "/chosen",
+ "linux,initrd-start", start);
+ qemu_fdt_setprop_cell(fdt, "/chosen",
+ "linux,initrd-end", start + size);
+ }
+
+ return start + size;
+}
+
+uint32_t openrisc_load_fdt(void *fdt, hwaddr load_start,
+ uint64_t mem_size)
+{
+ uint32_t fdt_addr;
+ int ret;
+ int fdtsize = fdt_totalsize(fdt);
+
+ if (fdtsize <= 0) {
+ error_report("invalid device-tree");
+ exit(1);
+ }
+
+ /* We put fdt right after the kernel and/or initrd. */
+ fdt_addr = TARGET_PAGE_ALIGN(load_start);
+
+ ret = fdt_pack(fdt);
+ /* Should only fail if we've built a corrupted tree */
+ g_assert(ret == 0);
+ /* copy in the device tree */
+ qemu_fdt_dumpdtb(fdt, fdtsize);
+
+ rom_add_blob_fixed_as("fdt", fdt, fdtsize, fdt_addr,
+ &address_space_memory);
+ qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds,
+ rom_ptr_for_as(&address_space_memory, fdt_addr, fdtsize));
+
+ return fdt_addr;
+}
diff --git a/hw/openrisc/cputimer.c b/hw/openrisc/cputimer.c
new file mode 100644
index 00000000..10163b39
--- /dev/null
+++ b/hw/openrisc/cputimer.c
@@ -0,0 +1,165 @@
+/*
+ * QEMU OpenRISC timer support
+ *
+ * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
+ * Zhizhou Zhang <etouzh@gmail.com>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "migration/vmstate.h"
+#include "qemu/timer.h"
+#include "sysemu/reset.h"
+
+#define TIMER_PERIOD 50 /* 50 ns period for 20 MHz timer */
+
+/* Tick Timer global state to allow all cores to be in sync */
+typedef struct OR1KTimerState {
+ uint32_t ttcr;
+ uint64_t last_clk;
+} OR1KTimerState;
+
+static OR1KTimerState *or1k_timer;
+
+void cpu_openrisc_count_set(OpenRISCCPU *cpu, uint32_t val)
+{
+ or1k_timer->ttcr = val;
+}
+
+uint32_t cpu_openrisc_count_get(OpenRISCCPU *cpu)
+{
+ return or1k_timer->ttcr;
+}
+
+/* Add elapsed ticks to ttcr */
+void cpu_openrisc_count_update(OpenRISCCPU *cpu)
+{
+ uint64_t now;
+
+ if (!cpu->env.is_counting) {
+ return;
+ }
+ now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+ or1k_timer->ttcr += (uint32_t)((now - or1k_timer->last_clk)
+ / TIMER_PERIOD);
+ or1k_timer->last_clk = now;
+}
+
+/* Update the next timeout time as difference between ttmr and ttcr */
+void cpu_openrisc_timer_update(OpenRISCCPU *cpu)
+{
+ uint32_t wait;
+ uint64_t now, next;
+
+ if (!cpu->env.is_counting) {
+ return;
+ }
+
+ cpu_openrisc_count_update(cpu);
+ now = or1k_timer->last_clk;
+
+ if ((cpu->env.ttmr & TTMR_TP) <= (or1k_timer->ttcr & TTMR_TP)) {
+ wait = TTMR_TP - (or1k_timer->ttcr & TTMR_TP) + 1;
+ wait += cpu->env.ttmr & TTMR_TP;
+ } else {
+ wait = (cpu->env.ttmr & TTMR_TP) - (or1k_timer->ttcr & TTMR_TP);
+ }
+ next = now + (uint64_t)wait * TIMER_PERIOD;
+ timer_mod(cpu->env.timer, next);
+}
+
+void cpu_openrisc_count_start(OpenRISCCPU *cpu)
+{
+ cpu->env.is_counting = 1;
+ cpu_openrisc_count_update(cpu);
+}
+
+void cpu_openrisc_count_stop(OpenRISCCPU *cpu)
+{
+ timer_del(cpu->env.timer);
+ cpu_openrisc_count_update(cpu);
+ cpu->env.is_counting = 0;
+}
+
+static void openrisc_timer_cb(void *opaque)
+{
+ OpenRISCCPU *cpu = opaque;
+
+ if ((cpu->env.ttmr & TTMR_IE) &&
+ timer_expired(cpu->env.timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL))) {
+ CPUState *cs = CPU(cpu);
+
+ cpu->env.ttmr |= TTMR_IP;
+ cs->interrupt_request |= CPU_INTERRUPT_TIMER;
+ }
+
+ switch (cpu->env.ttmr & TTMR_M) {
+ case TIMER_NONE:
+ break;
+ case TIMER_INTR:
+ or1k_timer->ttcr = 0;
+ break;
+ case TIMER_SHOT:
+ cpu_openrisc_count_stop(cpu);
+ break;
+ case TIMER_CONT:
+ break;
+ }
+
+ cpu_openrisc_timer_update(cpu);
+ qemu_cpu_kick(CPU(cpu));
+}
+
+/* Reset the per CPU counter state. */
+static void openrisc_count_reset(void *opaque)
+{
+ OpenRISCCPU *cpu = opaque;
+
+ if (cpu->env.is_counting) {
+ cpu_openrisc_count_stop(cpu);
+ }
+ cpu->env.ttmr = 0x00000000;
+}
+
+/* Reset the global timer state. */
+static void openrisc_timer_reset(void *opaque)
+{
+ or1k_timer->ttcr = 0x00000000;
+ or1k_timer->last_clk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+}
+
+static const VMStateDescription vmstate_or1k_timer = {
+ .name = "or1k_timer",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(ttcr, OR1KTimerState),
+ VMSTATE_UINT64(last_clk, OR1KTimerState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+void cpu_openrisc_clock_init(OpenRISCCPU *cpu)
+{
+ cpu->env.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &openrisc_timer_cb, cpu);
+
+ qemu_register_reset(openrisc_count_reset, cpu);
+ if (or1k_timer == NULL) {
+ or1k_timer = g_new0(OR1KTimerState, 1);
+ qemu_register_reset(openrisc_timer_reset, cpu);
+ vmstate_register(NULL, 0, &vmstate_or1k_timer, or1k_timer);
+ }
+}
diff --git a/hw/openrisc/meson.build b/hw/openrisc/meson.build
new file mode 100644
index 00000000..2dbc6365
--- /dev/null
+++ b/hw/openrisc/meson.build
@@ -0,0 +1,7 @@
+openrisc_ss = ss.source_set()
+openrisc_ss.add(files('cputimer.c'))
+openrisc_ss.add(files('boot.c'))
+openrisc_ss.add(when: 'CONFIG_OR1K_SIM', if_true: [files('openrisc_sim.c'), fdt])
+openrisc_ss.add(when: 'CONFIG_OR1K_VIRT', if_true: [files('virt.c'), fdt])
+
+hw_arch += {'openrisc': openrisc_ss}
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
new file mode 100644
index 00000000..35da123a
--- /dev/null
+++ b/hw/openrisc/openrisc_sim.c
@@ -0,0 +1,371 @@
+/*
+ * OpenRISC simulator for use as an IIS.
+ *
+ * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
+ * Feng Gao <gf91597@gmail.com>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/error-report.h"
+#include "qapi/error.h"
+#include "cpu.h"
+#include "hw/irq.h"
+#include "hw/boards.h"
+#include "hw/char/serial.h"
+#include "net/net.h"
+#include "hw/openrisc/boot.h"
+#include "hw/qdev-properties.h"
+#include "exec/address-spaces.h"
+#include "sysemu/device_tree.h"
+#include "sysemu/sysemu.h"
+#include "hw/sysbus.h"
+#include "sysemu/qtest.h"
+#include "sysemu/reset.h"
+#include "hw/core/split-irq.h"
+
+#include <libfdt.h>
+
+#define KERNEL_LOAD_ADDR 0x100
+
+#define OR1KSIM_CPUS_MAX 4
+#define OR1KSIM_CLK_MHZ 20000000
+
+#define TYPE_OR1KSIM_MACHINE MACHINE_TYPE_NAME("or1k-sim")
+#define OR1KSIM_MACHINE(obj) \
+ OBJECT_CHECK(Or1ksimState, (obj), TYPE_OR1KSIM_MACHINE)
+
+typedef struct Or1ksimState {
+ /*< private >*/
+ MachineState parent_obj;
+
+ /*< public >*/
+ void *fdt;
+ int fdt_size;
+
+} Or1ksimState;
+
+enum {
+ OR1KSIM_DRAM,
+ OR1KSIM_UART,
+ OR1KSIM_ETHOC,
+ OR1KSIM_OMPIC,
+};
+
+enum {
+ OR1KSIM_OMPIC_IRQ = 1,
+ OR1KSIM_UART_IRQ = 2,
+ OR1KSIM_ETHOC_IRQ = 4,
+};
+
+enum {
+ OR1KSIM_UART_COUNT = 4
+};
+
+static const struct MemmapEntry {
+ hwaddr base;
+ hwaddr size;
+} or1ksim_memmap[] = {
+ [OR1KSIM_DRAM] = { 0x00000000, 0 },
+ [OR1KSIM_UART] = { 0x90000000, 0x100 },
+ [OR1KSIM_ETHOC] = { 0x92000000, 0x800 },
+ [OR1KSIM_OMPIC] = { 0x98000000, OR1KSIM_CPUS_MAX * 8 },
+};
+
+static struct openrisc_boot_info {
+ uint32_t bootstrap_pc;
+ uint32_t fdt_addr;
+} boot_info;
+
+static void main_cpu_reset(void *opaque)
+{
+ OpenRISCCPU *cpu = opaque;
+ CPUState *cs = CPU(cpu);
+
+ cpu_reset(CPU(cpu));
+
+ cpu_set_pc(cs, boot_info.bootstrap_pc);
+ cpu_set_gpr(&cpu->env, 3, boot_info.fdt_addr);
+}
+
+static qemu_irq get_cpu_irq(OpenRISCCPU *cpus[], int cpunum, int irq_pin)
+{
+ return qdev_get_gpio_in_named(DEVICE(cpus[cpunum]), "IRQ", irq_pin);
+}
+
+static void openrisc_create_fdt(Or1ksimState *state,
+ const struct MemmapEntry *memmap,
+ int num_cpus, uint64_t mem_size,
+ const char *cmdline)
+{
+ void *fdt;
+ int cpu;
+ char *nodename;
+ int pic_ph;
+
+ fdt = state->fdt = create_device_tree(&state->fdt_size);
+ if (!fdt) {
+ error_report("create_device_tree() failed");
+ exit(1);
+ }
+
+ qemu_fdt_setprop_string(fdt, "/", "compatible", "opencores,or1ksim");
+ qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x1);
+ qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x1);
+
+ nodename = g_strdup_printf("/memory@%" HWADDR_PRIx,
+ memmap[OR1KSIM_DRAM].base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_cells(fdt, nodename, "reg",
+ memmap[OR1KSIM_DRAM].base, mem_size);
+ qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
+ g_free(nodename);
+
+ qemu_fdt_add_subnode(fdt, "/cpus");
+ qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
+ qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
+
+ for (cpu = 0; cpu < num_cpus; cpu++) {
+ nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible",
+ "opencores,or1200-rtlsvn481");
+ qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
+ qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
+ OR1KSIM_CLK_MHZ);
+ g_free(nodename);
+ }
+
+ nodename = (char *)"/pic";
+ qemu_fdt_add_subnode(fdt, nodename);
+ pic_ph = qemu_fdt_alloc_phandle(fdt);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible",
+ "opencores,or1k-pic-level");
+ qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
+ qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
+ qemu_fdt_setprop_cell(fdt, nodename, "phandle", pic_ph);
+
+ qemu_fdt_setprop_cell(fdt, "/", "interrupt-parent", pic_ph);
+
+ qemu_fdt_add_subnode(fdt, "/chosen");
+ if (cmdline) {
+ qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
+ }
+
+ /* Create aliases node for use by devices. */
+ qemu_fdt_add_subnode(fdt, "/aliases");
+}
+
+static void openrisc_sim_net_init(Or1ksimState *state, hwaddr base, hwaddr size,
+ int num_cpus, OpenRISCCPU *cpus[],
+ int irq_pin, NICInfo *nd)
+{
+ void *fdt = state->fdt;
+ DeviceState *dev;
+ SysBusDevice *s;
+ char *nodename;
+ int i;
+
+ dev = qdev_new("open_eth");
+ qdev_set_nic_properties(dev, nd);
+
+ s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
+ if (num_cpus > 1) {
+ DeviceState *splitter = qdev_new(TYPE_SPLIT_IRQ);
+ qdev_prop_set_uint32(splitter, "num-lines", num_cpus);
+ qdev_realize_and_unref(splitter, NULL, &error_fatal);
+ for (i = 0; i < num_cpus; i++) {
+ qdev_connect_gpio_out(splitter, i, get_cpu_irq(cpus, i, irq_pin));
+ }
+ sysbus_connect_irq(s, 0, qdev_get_gpio_in(splitter, 0));
+ } else {
+ sysbus_connect_irq(s, 0, get_cpu_irq(cpus, 0, irq_pin));
+ }
+ sysbus_mmio_map(s, 0, base);
+ sysbus_mmio_map(s, 1, base + 0x400);
+
+ /* Init device tree node for ethoc. */
+ nodename = g_strdup_printf("/ethoc@%" HWADDR_PRIx, base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "opencores,ethoc");
+ qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size);
+ qemu_fdt_setprop_cell(fdt, nodename, "interrupts", irq_pin);
+ qemu_fdt_setprop(fdt, nodename, "big-endian", NULL, 0);
+
+ qemu_fdt_setprop_string(fdt, "/aliases", "enet0", nodename);
+ g_free(nodename);
+}
+
+static void openrisc_sim_ompic_init(Or1ksimState *state, hwaddr base,
+ hwaddr size, int num_cpus,
+ OpenRISCCPU *cpus[], int irq_pin)
+{
+ void *fdt = state->fdt;
+ DeviceState *dev;
+ SysBusDevice *s;
+ char *nodename;
+ int i;
+
+ dev = qdev_new("or1k-ompic");
+ qdev_prop_set_uint32(dev, "num-cpus", num_cpus);
+
+ s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
+ for (i = 0; i < num_cpus; i++) {
+ sysbus_connect_irq(s, i, get_cpu_irq(cpus, i, irq_pin));
+ }
+ sysbus_mmio_map(s, 0, base);
+
+ /* Add device tree node for ompic. */
+ nodename = g_strdup_printf("/ompic@%" HWADDR_PRIx, base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "openrisc,ompic");
+ qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size);
+ qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
+ qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 0);
+ qemu_fdt_setprop_cell(fdt, nodename, "interrupts", irq_pin);
+ g_free(nodename);
+}
+
+static void openrisc_sim_serial_init(Or1ksimState *state, hwaddr base,
+ hwaddr size, int num_cpus,
+ OpenRISCCPU *cpus[], int irq_pin,
+ int uart_idx)
+{
+ void *fdt = state->fdt;
+ char *nodename;
+ qemu_irq serial_irq;
+ char alias[sizeof("uart0")];
+ int i;
+
+ if (num_cpus > 1) {
+ DeviceState *splitter = qdev_new(TYPE_SPLIT_IRQ);
+ qdev_prop_set_uint32(splitter, "num-lines", num_cpus);
+ qdev_realize_and_unref(splitter, NULL, &error_fatal);
+ for (i = 0; i < num_cpus; i++) {
+ qdev_connect_gpio_out(splitter, i, get_cpu_irq(cpus, i, irq_pin));
+ }
+ serial_irq = qdev_get_gpio_in(splitter, 0);
+ } else {
+ serial_irq = get_cpu_irq(cpus, 0, irq_pin);
+ }
+ serial_mm_init(get_system_memory(), base, 0, serial_irq, 115200,
+ serial_hd(OR1KSIM_UART_COUNT - uart_idx - 1),
+ DEVICE_NATIVE_ENDIAN);
+
+ /* Add device tree node for serial. */
+ nodename = g_strdup_printf("/serial@%" HWADDR_PRIx, base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "ns16550a");
+ qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size);
+ qemu_fdt_setprop_cell(fdt, nodename, "interrupts", irq_pin);
+ qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", OR1KSIM_CLK_MHZ);
+ qemu_fdt_setprop(fdt, nodename, "big-endian", NULL, 0);
+
+ /* The /chosen node is created during fdt creation. */
+ qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
+ snprintf(alias, sizeof(alias), "uart%d", uart_idx);
+ qemu_fdt_setprop_string(fdt, "/aliases", alias, nodename);
+ g_free(nodename);
+}
+
+static void openrisc_sim_init(MachineState *machine)
+{
+ ram_addr_t ram_size = machine->ram_size;
+ const char *kernel_filename = machine->kernel_filename;
+ OpenRISCCPU *cpus[OR1KSIM_CPUS_MAX] = {};
+ Or1ksimState *state = OR1KSIM_MACHINE(machine);
+ MemoryRegion *ram;
+ hwaddr load_addr;
+ int n;
+ unsigned int smp_cpus = machine->smp.cpus;
+
+ assert(smp_cpus >= 1 && smp_cpus <= OR1KSIM_CPUS_MAX);
+ for (n = 0; n < smp_cpus; n++) {
+ cpus[n] = OPENRISC_CPU(cpu_create(machine->cpu_type));
+ if (cpus[n] == NULL) {
+ fprintf(stderr, "Unable to find CPU definition!\n");
+ exit(1);
+ }
+
+ cpu_openrisc_clock_init(cpus[n]);
+
+ qemu_register_reset(main_cpu_reset, cpus[n]);
+ }
+
+ ram = g_malloc(sizeof(*ram));
+ memory_region_init_ram(ram, NULL, "openrisc.ram", ram_size, &error_fatal);
+ memory_region_add_subregion(get_system_memory(), 0, ram);
+
+ openrisc_create_fdt(state, or1ksim_memmap, smp_cpus, machine->ram_size,
+ machine->kernel_cmdline);
+
+ if (nd_table[0].used) {
+ openrisc_sim_net_init(state, or1ksim_memmap[OR1KSIM_ETHOC].base,
+ or1ksim_memmap[OR1KSIM_ETHOC].size,
+ smp_cpus, cpus,
+ OR1KSIM_ETHOC_IRQ, nd_table);
+ }
+
+ if (smp_cpus > 1) {
+ openrisc_sim_ompic_init(state, or1ksim_memmap[OR1KSIM_OMPIC].base,
+ or1ksim_memmap[OR1KSIM_OMPIC].size,
+ smp_cpus, cpus, OR1KSIM_OMPIC_IRQ);
+ }
+
+ for (n = 0; n < OR1KSIM_UART_COUNT; ++n)
+ openrisc_sim_serial_init(state, or1ksim_memmap[OR1KSIM_UART].base +
+ or1ksim_memmap[OR1KSIM_UART].size * n,
+ or1ksim_memmap[OR1KSIM_UART].size,
+ smp_cpus, cpus, OR1KSIM_UART_IRQ, n);
+
+ load_addr = openrisc_load_kernel(ram_size, kernel_filename,
+ &boot_info.bootstrap_pc);
+ if (load_addr > 0) {
+ if (machine->initrd_filename) {
+ load_addr = openrisc_load_initrd(state->fdt,
+ machine->initrd_filename,
+ load_addr, machine->ram_size);
+ }
+ boot_info.fdt_addr = openrisc_load_fdt(state->fdt, load_addr,
+ machine->ram_size);
+ }
+}
+
+static void openrisc_sim_machine_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ mc->desc = "or1k simulation";
+ mc->init = openrisc_sim_init;
+ mc->max_cpus = OR1KSIM_CPUS_MAX;
+ mc->is_default = true;
+ mc->default_cpu_type = OPENRISC_CPU_TYPE_NAME("or1200");
+}
+
+static const TypeInfo or1ksim_machine_typeinfo = {
+ .name = TYPE_OR1KSIM_MACHINE,
+ .parent = TYPE_MACHINE,
+ .class_init = openrisc_sim_machine_init,
+ .instance_size = sizeof(Or1ksimState),
+};
+
+static void or1ksim_machine_init_register_types(void)
+{
+ type_register_static(&or1ksim_machine_typeinfo);
+}
+
+type_init(or1ksim_machine_init_register_types)
diff --git a/hw/openrisc/virt.c b/hw/openrisc/virt.c
new file mode 100644
index 00000000..f8a68a6a
--- /dev/null
+++ b/hw/openrisc/virt.c
@@ -0,0 +1,571 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * OpenRISC QEMU virtual machine.
+ *
+ * (c) 2022 Stafford Horne <shorne@gmail.com>
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/error-report.h"
+#include "qemu/guest-random.h"
+#include "qapi/error.h"
+#include "cpu.h"
+#include "exec/address-spaces.h"
+#include "hw/irq.h"
+#include "hw/boards.h"
+#include "hw/char/serial.h"
+#include "hw/core/split-irq.h"
+#include "hw/openrisc/boot.h"
+#include "hw/misc/sifive_test.h"
+#include "hw/pci/pci.h"
+#include "hw/pci-host/gpex.h"
+#include "hw/qdev-properties.h"
+#include "hw/rtc/goldfish_rtc.h"
+#include "hw/sysbus.h"
+#include "hw/virtio/virtio-mmio.h"
+#include "sysemu/device_tree.h"
+#include "sysemu/sysemu.h"
+#include "sysemu/qtest.h"
+#include "sysemu/reset.h"
+
+#include <libfdt.h>
+
+#define VIRT_CPUS_MAX 4
+#define VIRT_CLK_MHZ 20000000
+
+#define TYPE_VIRT_MACHINE MACHINE_TYPE_NAME("virt")
+#define VIRT_MACHINE(obj) \
+ OBJECT_CHECK(OR1KVirtState, (obj), TYPE_VIRT_MACHINE)
+
+typedef struct OR1KVirtState {
+ /*< private >*/
+ MachineState parent_obj;
+
+ /*< public >*/
+ void *fdt;
+ int fdt_size;
+
+} OR1KVirtState;
+
+enum {
+ VIRT_DRAM,
+ VIRT_ECAM,
+ VIRT_MMIO,
+ VIRT_PIO,
+ VIRT_TEST,
+ VIRT_RTC,
+ VIRT_VIRTIO,
+ VIRT_UART,
+ VIRT_OMPIC,
+};
+
+enum {
+ VIRT_OMPIC_IRQ = 1,
+ VIRT_UART_IRQ = 2,
+ VIRT_RTC_IRQ = 3,
+ VIRT_VIRTIO_IRQ = 4, /* to 12 */
+ VIRTIO_COUNT = 8,
+ VIRT_PCI_IRQ_BASE = 13, /* to 17 */
+};
+
+static const struct MemmapEntry {
+ hwaddr base;
+ hwaddr size;
+} virt_memmap[] = {
+ [VIRT_DRAM] = { 0x00000000, 0 },
+ [VIRT_UART] = { 0x90000000, 0x100 },
+ [VIRT_TEST] = { 0x96000000, 0x8 },
+ [VIRT_RTC] = { 0x96005000, 0x1000 },
+ [VIRT_VIRTIO] = { 0x97000000, 0x1000 },
+ [VIRT_OMPIC] = { 0x98000000, VIRT_CPUS_MAX * 8 },
+ [VIRT_ECAM] = { 0x9e000000, 0x1000000 },
+ [VIRT_PIO] = { 0x9f000000, 0x1000000 },
+ [VIRT_MMIO] = { 0xa0000000, 0x10000000 },
+};
+
+static struct openrisc_boot_info {
+ uint32_t bootstrap_pc;
+ uint32_t fdt_addr;
+} boot_info;
+
+static void main_cpu_reset(void *opaque)
+{
+ OpenRISCCPU *cpu = opaque;
+ CPUState *cs = CPU(cpu);
+
+ cpu_reset(CPU(cpu));
+
+ cpu_set_pc(cs, boot_info.bootstrap_pc);
+ cpu_set_gpr(&cpu->env, 3, boot_info.fdt_addr);
+}
+
+static qemu_irq get_cpu_irq(OpenRISCCPU *cpus[], int cpunum, int irq_pin)
+{
+ return qdev_get_gpio_in_named(DEVICE(cpus[cpunum]), "IRQ", irq_pin);
+}
+
+static qemu_irq get_per_cpu_irq(OpenRISCCPU *cpus[], int num_cpus, int irq_pin)
+{
+ int i;
+
+ if (num_cpus > 1) {
+ DeviceState *splitter = qdev_new(TYPE_SPLIT_IRQ);
+ qdev_prop_set_uint32(splitter, "num-lines", num_cpus);
+ qdev_realize_and_unref(splitter, NULL, &error_fatal);
+ for (i = 0; i < num_cpus; i++) {
+ qdev_connect_gpio_out(splitter, i, get_cpu_irq(cpus, i, irq_pin));
+ }
+ return qdev_get_gpio_in(splitter, 0);
+ } else {
+ return get_cpu_irq(cpus, 0, irq_pin);
+ }
+}
+
+static void openrisc_create_fdt(OR1KVirtState *state,
+ const struct MemmapEntry *memmap,
+ int num_cpus, uint64_t mem_size,
+ const char *cmdline,
+ int32_t *pic_phandle)
+{
+ void *fdt;
+ int cpu;
+ char *nodename;
+ uint8_t rng_seed[32];
+
+ fdt = state->fdt = create_device_tree(&state->fdt_size);
+ if (!fdt) {
+ error_report("create_device_tree() failed");
+ exit(1);
+ }
+
+ qemu_fdt_setprop_string(fdt, "/", "compatible", "opencores,or1ksim");
+ qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x1);
+ qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x1);
+
+ qemu_fdt_add_subnode(fdt, "/soc");
+ qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
+ qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
+ qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x1);
+ qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x1);
+
+ nodename = g_strdup_printf("/memory@%" HWADDR_PRIx,
+ memmap[VIRT_DRAM].base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_cells(fdt, nodename, "reg",
+ memmap[VIRT_DRAM].base, mem_size);
+ qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
+ g_free(nodename);
+
+ qemu_fdt_add_subnode(fdt, "/cpus");
+ qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
+ qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
+
+ for (cpu = 0; cpu < num_cpus; cpu++) {
+ nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible",
+ "opencores,or1200-rtlsvn481");
+ qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
+ qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
+ VIRT_CLK_MHZ);
+ g_free(nodename);
+ }
+
+ nodename = (char *)"/pic";
+ qemu_fdt_add_subnode(fdt, nodename);
+ *pic_phandle = qemu_fdt_alloc_phandle(fdt);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible",
+ "opencores,or1k-pic-level");
+ qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
+ qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
+ qemu_fdt_setprop_cell(fdt, nodename, "phandle", *pic_phandle);
+
+ qemu_fdt_setprop_cell(fdt, "/", "interrupt-parent", *pic_phandle);
+
+ qemu_fdt_add_subnode(fdt, "/chosen");
+ if (cmdline) {
+ qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
+ }
+
+ /* Pass seed to RNG. */
+ qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed));
+ qemu_fdt_setprop(fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed));
+
+ /* Create aliases node for use by devices. */
+ qemu_fdt_add_subnode(fdt, "/aliases");
+}
+
+static void openrisc_virt_ompic_init(OR1KVirtState *state, hwaddr base,
+ hwaddr size, int num_cpus,
+ OpenRISCCPU *cpus[], int irq_pin)
+{
+ void *fdt = state->fdt;
+ DeviceState *dev;
+ SysBusDevice *s;
+ char *nodename;
+ int i;
+
+ dev = qdev_new("or1k-ompic");
+ qdev_prop_set_uint32(dev, "num-cpus", num_cpus);
+
+ s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
+ for (i = 0; i < num_cpus; i++) {
+ sysbus_connect_irq(s, i, get_cpu_irq(cpus, i, irq_pin));
+ }
+ sysbus_mmio_map(s, 0, base);
+
+ /* Add device tree node for ompic. */
+ nodename = g_strdup_printf("/ompic@%" HWADDR_PRIx, base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "openrisc,ompic");
+ qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size);
+ qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
+ qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 0);
+ qemu_fdt_setprop_cell(fdt, nodename, "interrupts", irq_pin);
+ g_free(nodename);
+}
+
+static void openrisc_virt_serial_init(OR1KVirtState *state, hwaddr base,
+ hwaddr size, int num_cpus,
+ OpenRISCCPU *cpus[], int irq_pin)
+{
+ void *fdt = state->fdt;
+ char *nodename;
+ qemu_irq serial_irq = get_per_cpu_irq(cpus, num_cpus, irq_pin);
+
+ serial_mm_init(get_system_memory(), base, 0, serial_irq, 115200,
+ serial_hd(0), DEVICE_NATIVE_ENDIAN);
+
+ /* Add device tree node for serial. */
+ nodename = g_strdup_printf("/serial@%" HWADDR_PRIx, base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "ns16550a");
+ qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size);
+ qemu_fdt_setprop_cell(fdt, nodename, "interrupts", irq_pin);
+ qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", VIRT_CLK_MHZ);
+ qemu_fdt_setprop(fdt, nodename, "big-endian", NULL, 0);
+
+ /* The /chosen node is created during fdt creation. */
+ qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
+ qemu_fdt_setprop_string(fdt, "/aliases", "uart0", nodename);
+ g_free(nodename);
+}
+
+static void openrisc_virt_test_init(OR1KVirtState *state, hwaddr base,
+ hwaddr size)
+{
+ void *fdt = state->fdt;
+ int test_ph;
+ char *nodename;
+
+ /* SiFive Test MMIO device */
+ sifive_test_create(base);
+
+ /* SiFive Test MMIO Reset device FDT */
+ nodename = g_strdup_printf("/soc/test@%" HWADDR_PRIx, base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "syscon");
+ test_ph = qemu_fdt_alloc_phandle(fdt);
+ qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size);
+ qemu_fdt_setprop_cell(fdt, nodename, "phandle", test_ph);
+ qemu_fdt_setprop(fdt, nodename, "big-endian", NULL, 0);
+ g_free(nodename);
+
+ nodename = g_strdup_printf("/soc/reboot");
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "syscon-reboot");
+ qemu_fdt_setprop_cell(fdt, nodename, "regmap", test_ph);
+ qemu_fdt_setprop_cell(fdt, nodename, "offset", 0x0);
+ qemu_fdt_setprop_cell(fdt, nodename, "value", FINISHER_RESET);
+ g_free(nodename);
+
+ nodename = g_strdup_printf("/soc/poweroff");
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "syscon-poweroff");
+ qemu_fdt_setprop_cell(fdt, nodename, "regmap", test_ph);
+ qemu_fdt_setprop_cell(fdt, nodename, "offset", 0x0);
+ qemu_fdt_setprop_cell(fdt, nodename, "value", FINISHER_PASS);
+ g_free(nodename);
+
+}
+
+static void openrisc_virt_rtc_init(OR1KVirtState *state, hwaddr base,
+ hwaddr size, int num_cpus,
+ OpenRISCCPU *cpus[], int irq_pin)
+{
+ void *fdt = state->fdt;
+ char *nodename;
+ qemu_irq rtc_irq = get_per_cpu_irq(cpus, num_cpus, irq_pin);
+
+ /* Goldfish RTC */
+ sysbus_create_simple(TYPE_GOLDFISH_RTC, base, rtc_irq);
+
+ /* Goldfish RTC FDT */
+ nodename = g_strdup_printf("/soc/rtc@%" HWADDR_PRIx, base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible",
+ "google,goldfish-rtc");
+ qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size);
+ qemu_fdt_setprop_cell(fdt, nodename, "interrupts", irq_pin);
+ g_free(nodename);
+
+}
+
+static void create_pcie_irq_map(void *fdt, char *nodename, int irq_base,
+ uint32_t irqchip_phandle)
+{
+ int pin, dev;
+ uint32_t irq_map_stride = 0;
+ uint32_t full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * 6] = {};
+ uint32_t *irq_map = full_irq_map;
+
+ /*
+ * This code creates a standard swizzle of interrupts such that
+ * each device's first interrupt is based on it's PCI_SLOT number.
+ * (See pci_swizzle_map_irq_fn())
+ *
+ * We only need one entry per interrupt in the table (not one per
+ * possible slot) seeing the interrupt-map-mask will allow the table
+ * to wrap to any number of devices.
+ */
+ for (dev = 0; dev < GPEX_NUM_IRQS; dev++) {
+ int devfn = dev << 3;
+
+ for (pin = 0; pin < GPEX_NUM_IRQS; pin++) {
+ int irq_nr = irq_base + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS);
+ int i = 0;
+
+ /* Fill PCI address cells */
+ irq_map[i++] = cpu_to_be32(devfn << 8);
+ irq_map[i++] = 0;
+ irq_map[i++] = 0;
+
+ /* Fill PCI Interrupt cells */
+ irq_map[i++] = cpu_to_be32(pin + 1);
+
+ /* Fill interrupt controller phandle and cells */
+ irq_map[i++] = cpu_to_be32(irqchip_phandle);
+ irq_map[i++] = cpu_to_be32(irq_nr);
+
+ if (!irq_map_stride) {
+ irq_map_stride = i;
+ }
+ irq_map += irq_map_stride;
+ }
+ }
+
+ qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map,
+ GPEX_NUM_IRQS * GPEX_NUM_IRQS *
+ irq_map_stride * sizeof(uint32_t));
+
+ qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask",
+ 0x1800, 0, 0, 0x7);
+}
+
+static void openrisc_virt_pcie_init(OR1KVirtState *state,
+ hwaddr ecam_base, hwaddr ecam_size,
+ hwaddr pio_base, hwaddr pio_size,
+ hwaddr mmio_base, hwaddr mmio_size,
+ int num_cpus, OpenRISCCPU *cpus[],
+ int irq_base, int32_t pic_phandle)
+{
+ void *fdt = state->fdt;
+ char *nodename;
+ MemoryRegion *alias;
+ MemoryRegion *reg;
+ DeviceState *dev;
+ qemu_irq pcie_irq;
+ int i;
+
+ dev = qdev_new(TYPE_GPEX_HOST);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+
+ /* Map ECAM space. */
+ alias = g_new0(MemoryRegion, 1);
+ reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
+ memory_region_init_alias(alias, OBJECT(dev), "pcie-ecam",
+ reg, 0, ecam_size);
+ memory_region_add_subregion(get_system_memory(), ecam_base, alias);
+
+ /*
+ * Map the MMIO window into system address space so as to expose
+ * the section of PCI MMIO space which starts at the same base address
+ * (ie 1:1 mapping for that part of PCI MMIO space visible through
+ * the window).
+ */
+ alias = g_new0(MemoryRegion, 1);
+ reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
+ memory_region_init_alias(alias, OBJECT(dev), "pcie-mmio",
+ reg, mmio_base, mmio_size);
+ memory_region_add_subregion(get_system_memory(), mmio_base, alias);
+
+ /* Map IO port space. */
+ alias = g_new0(MemoryRegion, 1);
+ reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 2);
+ memory_region_init_alias(alias, OBJECT(dev), "pcie-pio",
+ reg, 0, pio_size);
+ memory_region_add_subregion(get_system_memory(), pio_base, alias);
+
+ /* Connect IRQ lines. */
+ for (i = 0; i < GPEX_NUM_IRQS; i++) {
+ pcie_irq = get_per_cpu_irq(cpus, num_cpus, irq_base + i);
+
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pcie_irq);
+ gpex_set_irq_num(GPEX_HOST(dev), i, irq_base + i);
+ }
+
+ nodename = g_strdup_printf("/soc/pci@%" HWADDR_PRIx, ecam_base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
+ qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 3);
+ qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 2);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible",
+ "pci-host-ecam-generic");
+ qemu_fdt_setprop_string(fdt, nodename, "device_type", "pci");
+ qemu_fdt_setprop_cell(fdt, nodename, "linux,pci-domain", 0);
+ qemu_fdt_setprop_cells(fdt, nodename, "bus-range", 0,
+ ecam_size / PCIE_MMCFG_SIZE_MIN - 1);
+ qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0);
+ qemu_fdt_setprop_cells(fdt, nodename, "reg", ecam_base, ecam_size);
+ /* pci-address(3) cpu-address(1) pci-size(2) */
+ qemu_fdt_setprop_cells(fdt, nodename, "ranges",
+ FDT_PCI_RANGE_IOPORT, 0, 0,
+ pio_base, 0, pio_size,
+ FDT_PCI_RANGE_MMIO, 0, mmio_base,
+ mmio_base, 0, mmio_size);
+
+ create_pcie_irq_map(fdt, nodename, irq_base, pic_phandle);
+ g_free(nodename);
+}
+
+static void openrisc_virt_virtio_init(OR1KVirtState *state, hwaddr base,
+ hwaddr size, int num_cpus,
+ OpenRISCCPU *cpus[], int irq_pin)
+{
+ void *fdt = state->fdt;
+ char *nodename;
+ DeviceState *dev;
+ SysBusDevice *sysbus;
+ qemu_irq virtio_irq = get_per_cpu_irq(cpus, num_cpus, irq_pin);
+
+ /* VirtIO MMIO devices */
+ dev = qdev_new(TYPE_VIRTIO_MMIO);
+ qdev_prop_set_bit(dev, "force-legacy", false);
+ sysbus = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(sysbus, &error_fatal);
+ sysbus_connect_irq(sysbus, 0, virtio_irq);
+ sysbus_mmio_map(sysbus, 0, base);
+
+ /* VirtIO MMIO devices FDT */
+ nodename = g_strdup_printf("/soc/virtio_mmio@%" HWADDR_PRIx, base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "virtio,mmio");
+ qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size);
+ qemu_fdt_setprop_cell(fdt, nodename, "interrupts", irq_pin);
+ g_free(nodename);
+}
+
+static void openrisc_virt_init(MachineState *machine)
+{
+ ram_addr_t ram_size = machine->ram_size;
+ const char *kernel_filename = machine->kernel_filename;
+ OpenRISCCPU *cpus[VIRT_CPUS_MAX] = {};
+ OR1KVirtState *state = VIRT_MACHINE(machine);
+ MemoryRegion *ram;
+ hwaddr load_addr;
+ int n;
+ unsigned int smp_cpus = machine->smp.cpus;
+ int32_t pic_phandle;
+
+ assert(smp_cpus >= 1 && smp_cpus <= VIRT_CPUS_MAX);
+ for (n = 0; n < smp_cpus; n++) {
+ cpus[n] = OPENRISC_CPU(cpu_create(machine->cpu_type));
+ if (cpus[n] == NULL) {
+ fprintf(stderr, "Unable to find CPU definition!\n");
+ exit(1);
+ }
+
+ cpu_openrisc_clock_init(cpus[n]);
+
+ qemu_register_reset(main_cpu_reset, cpus[n]);
+ }
+
+ ram = g_malloc(sizeof(*ram));
+ memory_region_init_ram(ram, NULL, "openrisc.ram", ram_size, &error_fatal);
+ memory_region_add_subregion(get_system_memory(), 0, ram);
+
+ openrisc_create_fdt(state, virt_memmap, smp_cpus, machine->ram_size,
+ machine->kernel_cmdline, &pic_phandle);
+
+ if (smp_cpus > 1) {
+ openrisc_virt_ompic_init(state, virt_memmap[VIRT_OMPIC].base,
+ virt_memmap[VIRT_OMPIC].size,
+ smp_cpus, cpus, VIRT_OMPIC_IRQ);
+ }
+
+ openrisc_virt_serial_init(state, virt_memmap[VIRT_UART].base,
+ virt_memmap[VIRT_UART].size,
+ smp_cpus, cpus, VIRT_UART_IRQ);
+
+ openrisc_virt_test_init(state, virt_memmap[VIRT_TEST].base,
+ virt_memmap[VIRT_TEST].size);
+
+ openrisc_virt_rtc_init(state, virt_memmap[VIRT_RTC].base,
+ virt_memmap[VIRT_RTC].size, smp_cpus, cpus,
+ VIRT_RTC_IRQ);
+
+ openrisc_virt_pcie_init(state, virt_memmap[VIRT_ECAM].base,
+ virt_memmap[VIRT_ECAM].size,
+ virt_memmap[VIRT_PIO].base,
+ virt_memmap[VIRT_PIO].size,
+ virt_memmap[VIRT_MMIO].base,
+ virt_memmap[VIRT_MMIO].size,
+ smp_cpus, cpus,
+ VIRT_PCI_IRQ_BASE, pic_phandle);
+
+ for (n = 0; n < VIRTIO_COUNT; n++) {
+ openrisc_virt_virtio_init(state, virt_memmap[VIRT_VIRTIO].base
+ + n * virt_memmap[VIRT_VIRTIO].size,
+ virt_memmap[VIRT_VIRTIO].size,
+ smp_cpus, cpus, VIRT_VIRTIO_IRQ + n);
+ }
+
+ load_addr = openrisc_load_kernel(ram_size, kernel_filename,
+ &boot_info.bootstrap_pc);
+ if (load_addr > 0) {
+ if (machine->initrd_filename) {
+ load_addr = openrisc_load_initrd(state->fdt,
+ machine->initrd_filename,
+ load_addr, machine->ram_size);
+ }
+ boot_info.fdt_addr = openrisc_load_fdt(state->fdt, load_addr,
+ machine->ram_size);
+ }
+}
+
+static void openrisc_virt_machine_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ mc->desc = "or1k virtual machine";
+ mc->init = openrisc_virt_init;
+ mc->max_cpus = VIRT_CPUS_MAX;
+ mc->is_default = false;
+ mc->default_cpu_type = OPENRISC_CPU_TYPE_NAME("or1200");
+}
+
+static const TypeInfo or1ksim_machine_typeinfo = {
+ .name = TYPE_VIRT_MACHINE,
+ .parent = TYPE_MACHINE,
+ .class_init = openrisc_virt_machine_init,
+ .instance_size = sizeof(OR1KVirtState),
+};
+
+static void or1ksim_machine_init_register_types(void)
+{
+ type_register_static(&or1ksim_machine_typeinfo);
+}
+
+type_init(or1ksim_machine_init_register_types)
generated by cgit v1.2.3 (git 2.39.1) at 2025-07-28 14:59:35 +0000