diff options
| author | Daniel Baumann <mail@daniel-baumann.ch> | 2025-06-06 10:05:23 +0000 |
|---|---|---|
| committer | Daniel Baumann <mail@daniel-baumann.ch> | 2025-06-06 10:05:23 +0000 |
| commit | 755cc582a2473d06f3a2131d506d0311cc70e9f9 (patch) | |
| tree | 3efb1ddb8d57bbb4539ac0d229b384871c57820f /docs/system/openrisc/cpu-features.rst | |
| parent | Initial commit. (diff) | |
| download | qemu-upstream.tar.xz qemu-upstream.zip | |
Adding upstream version 1:7.2+dfsg.upstream/1%7.2+dfsgupstream
Signed-off-by: Daniel Baumann <mail@daniel-baumann.ch>
Diffstat (limited to 'docs/system/openrisc/cpu-features.rst')
| -rw-r--r-- | docs/system/openrisc/cpu-features.rst | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/docs/system/openrisc/cpu-features.rst b/docs/system/openrisc/cpu-features.rst new file mode 100644 index 00000000..aeb65e22 --- /dev/null +++ b/docs/system/openrisc/cpu-features.rst @@ -0,0 +1,15 @@ +CPU Features +============ + +The QEMU emulation of the OpenRISC architecture provides following built in +features. + +- Shadow GPRs +- MMU TLB with 128 entries, 1 way +- Power Management (PM) +- Programmable Interrupt Controller (PIC) +- Tick Timer + +These features are on by default and the presence can be confirmed by checking +the contents of the Unit Presence Register (``UPR``) and CPU Configuration +Register (``CPUCFGR``). |